Inlet for an electronic tag

ABSTRACT

Provided are an inlet for an electronic tag comprising an insulating film, antennas each made of a conductor layer and formed over one surface of the insulating film, a slit formed in a portion of each of the antennas and having one end extending toward the outer edge of the antenna, a semiconductor chip electrically connected with each of the antennas via a plurality of bump electrodes, and a resin for sealing the semiconductor chip therewith; and a manufacturing process of the inlet. By the present invention, formation of a thin and highly-reliable inlet for a non-contact type electronic tag can be actualized.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to an inlet for a non-contact typeelectronic tag, particularly to a technique effective when applied tothinning and reliability increase of the inlet for an electronic tag.

[0002] A non-contact type electronic tag is a device capable of storingdesired information in a memory circuit of a semiconductor chip and fromthe tag, the necessary information is read by means of microwaves.

[0003] One example of such a non-contact type electronic tag isdisclosed in Japanese Patent Laid-Open No. Hei 10(1998)-13296 (PatentDocument 1). The electronic tag has a microwave receiving antenna formedof a lead frame on which a packaged semiconductor chip has been sealedwith a resin. [Patent Document 1]

[0004] Japanese Patent Laid-Open No. Hei 10(1998)-13296

SUMMARY OF THE INVENTION

[0005] An electronic tag has an advantage of storing large volumes ofdata compared with a tag using a bar code, because the electronic tagstores data in a memory circuit of a semiconductor chip. Anotheradvantage is that the data stored in the memory circuit cannot befalsified easily compared with the data stored in the bar code.

[0006] Such an electronic tag however has a structure more complex thanthat of the tag using a bar code and its manufacturing cost inevitablyincreases, which has been one cause for preventing popular use of theelectronic tag.

[0007] The present inventors have therefore proceeded with thedevelopment of an inlet for an electronic tag which has a simplifiedstructure and therefore can be produced at a lower cost. This inlet hasa structure in which a semiconductor chip is mounted on an antennaformed of a lead frame, the antenna is electrically connected to thesemiconductor chip via an Au wire and the semiconductor chip and Au wireare sealed with a potting resin.

[0008] In the above-described inlet, however, the antenna formed of alead frame and the semiconductor chip are connected via an Au wire. Whenthe semiconductor chip and the Au wire are sealed with a potting resin,the total inlet thickness inevitably reaches about 0.6 mm, which causesproblems that the resulting inlet cannot satisfy the demand forthinning, or cannot have sufficient flexibility against bendingdeformation at the antenna part.

[0009] An object of the present invention is to provide a techniquecapable of actualizing thinning and reliability increase of an inlet foran electronic tag.

[0010] Another object of the present invention is to provide a techniquecapable of actualizing an inlet tag for an electronic tag which is thin,highly flexible and inexpensive.

[0011] The above-described and the other objects, and novel features ofthe present invention will become apparent from the description hereinand accompanying drawings.

[0012] The outline of the typical inventions, among the inventionsdisclosed by the present application, will next be explained briefly.

[0013] An inlet for an electronic tag according to the present inventionis equipped with an insulating film, an antenna made of a conductorlayer and formed over one surface of the insulating film, a slit formedin a portion of the antenna and having one end extending to the outeredge of the antenna, a semiconductor chip electrically connected to theantenna via a plurality of bump electrodes, and a resin for sealing thesemiconductor chip therewith.

[0014] In the above-described inlet for an electronic tag according tothe present invention, a cutout for exposing the insulating film isdisposed in a portion of the antenna; a plurality of lead patterns madeof the conductor film is disposed inside of the cutout, each having oneend connected to the antenna and the other end extending inside of thecutout; and the plurality of bump electrodes are connected respectivelyto the surfaces of the lead patterns formed at positions correspondingto the bump electrodes.

[0015] A manufacturing process of the inlet for an electronic tagcomprises (a) preparing a long insulating film in which a plurality ofantennas made of a conductor layer are formed so as to be separated fromeach other; (b) connecting semiconductor chips to the plurality ofantennas formed in the insulating film, respectively; (c) sealing thesemiconductor chips connected respectively to the plurality of antennaswith a resin; and (d) checking the quality of the inlet for anelectronic tag manufactured by the steps (a), (b) and (c), wherein thelong insulating film is carried from the step (a) to the step (d) whilebeing wound onto a reel.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016]FIG. 1 is a plan view (on the surface side) illustrating an inletfor an electronic tag according to one embodiment of the presentinvention;

[0017]FIG. 2 is a plan view in which a portion of FIG. 1 is illustratedin an enlarged form;

[0018]FIG. 3 is a side view illustrating the inlet for an electronic tagaccording to the one embodiment of the present invention;

[0019]FIG. 4 is a plan view (on the back side) illustrating the inletfor an electronic tag according to the one embodiment of the presentinvention;

[0020]FIG. 5 is a plan view in which a portion of FIG. 4 is illustratedin an enlarged form;

[0021]FIG. 6 is a fragmentary enlarged plan view (on the surface side)illustrating the inlet for an electronic tag according to the oneembodiment of the present invention;

[0022]FIG. 7 is a fragmentary enlarged plan view (on the back side)illustrating the inlet for the electronic tag according to the oneembodiment of the present invention;

[0023]FIG. 8 is a plan view of a semiconductor chip mounted on the inletfor an electronic tag according to the one embodiment of the presentinvention;

[0024]FIG. 9 is a cross-sectional view of a bump electrode formed overthe main surface of the semiconductor chip as illustrated in FIG. 8 andthe vicinity of the bump electrode;

[0025]FIG. 10 is a cross-sectional view of a dummy bump electrode formedover the main surface of the semiconductor chip as illustrated in FIG. 8and the vicinity of the electrode;

[0026]FIG. 11 is a block diagram of a circuit formed over the mainsurface of the semiconductor chip illustrated in FIG. 8;

[0027]FIG. 12 is a plan view illustrating a portion of a long insulatingfilm to be used for the manufacture of the inlet for an electronic tagaccording to the one embodiment of the present invention;

[0028]FIG. 13 is an enlarged plan view of a portion of the insulatingfilm as illustrated in FIG. 12;

[0029]FIG. 14 is a schematic view of an inner lead bonder illustratingone (step for connecting the semiconductor chip to the antenna) of themanufacturing steps of the inlet for an electronic tag according to theone embodiment of the present invention;

[0030]FIG. 15 is a fragmentary enlarged schematic view of the inner leadbonder as illustrated in FIG. 14;

[0031]FIG. 16 is a fragmentary enlarged plan view of the insulating filmillustrating one (step for connecting the semiconductor chip to theantenna) of the manufacturing steps of the inlet for an electronic tagaccording to the one embodiment of the present invention;

[0032]FIG. 17 is a fragmentary enlarged plan view of the insulating filmillustrating one (step for connecting the semiconductor chip to theantenna) of the manufacturing steps of the inlet for an electronic tagaccording to the one embodiment of the present invention;

[0033]FIG. 18 is a schematic view illustrating one (a step for sealingthe semiconductor chip with a resin) of the manufacturing steps of theinlet for an electronic tag according to the one embodiment of thepresent invention;

[0034]FIG. 19 is a fragmentary enlarged plan view of the insulating filmillustrating one (step for sealing the semiconductor chip with a resin)of the manufacturing steps of the inlet for an electronic tag accordingto the one embodiment of the present invention;

[0035]FIG. 20 is a side view illustrating the insulating film in theform wound onto a reel, which film is to be used for the manufacture ofthe inlet for an electronic tag according to the one embodiment of thepresent invention;

[0036]FIG. 21 is an explanatory view illustrating a using method of anelectronic tag by using the inlet for an electronic tag according to theone embodiment of the present invention;

[0037]FIG. 22 is a fragmentary enlarged cross-sectional view of theinsulating film illustrating a part (a step for connecting thesemiconductor chip to the antenna) of the manufacturing steps of aninlet for an electronic tag according to another embodiment of thepresent invention;

[0038]FIG. 23 is a fragmentary enlarged cross-sectional view of theinsulating film illustrating one (a step for connecting thesemiconductor chip to the antenna) of the manufacturing steps of theinlet for an electronic tag according to the another embodiment of thepresent invention;

[0039]FIG. 24 is a plan view illustrating a portion of the longinsulating film to be used for the manufacture of the inlet for anelectronic tag according to the another embodiment of the presentinvention;

[0040]FIG. 25 is an enlarged plan view illustrating a portion of theantenna formed in the insulating film as illustrated in FIG. 24;

[0041]FIG. 26 is a flow chart illustrating the manufacturing steps ofthe inlet for an electronic tag according to the another embodiment ofthe present invention;

[0042]FIG. 27 is a schematic view of an inner lead bonder, illustratingone (a step for connecting the semiconductor chip to the antenna) of themanufacturing steps of the inlet for an electronic tag according to theanother embodiment of the present invention;

[0043]FIG. 28 is a fragmentary enlarged schematic view of the inner leadbonder as illustrated in FIG. 27;

[0044]FIG. 29 is a plan view illustrating how the Au bumps and leadpatterns of the semiconductor chip are overlapped each other;

[0045]FIG. 30 is a plan view illustrating how the Au bumps and leadpatterns are overlapped in Comparative Example;

[0046]FIG. 31 is a plan view illustrating how the Au bumps and leadpatterns are overlapped in another Comparative Example;

[0047]FIG. 32 is a schematic view illustrating one (a step for sealingthe semiconductor chip with a resin) of the manufacturing steps of theinlet for an electronic tag according to the another embodiment of thepresent invention;

[0048]FIG. 33 is a plan view illustrating one example of a relationbetween the size of the cutout formed in one portion of the antenna andthe size of the resin for sealing the semiconductor chip;

[0049]FIG. 34 is a plan view illustrating another example of a relationbetween the size of the cutout formed in one portion of the antenna andthe size of the resin for sealing the semiconductor chip; and

[0050]FIG. 35 is a plan view illustrating one example of a relationamong the size of the cutout formed in one portion of the antenna, thesize of the semiconductor chip, and the size of the resin for sealingthe semiconductor chip.

DETAILED DESCRIPTION OF THE INVENTION

[0051] The embodiments of the present invention will hereinafter bedescribed specifically based on accompanying drawings. In all thedrawings for describing the below-described embodiments, members havinglike function will be identified by like reference numerals andoverlapping descriptions will be omitted.

[0052] (Embodiment 1)

[0053]FIG. 1 is a plan view (on the surface side) illustrating an inletfor an electronic tag according to this embodiment of the presentinvention; FIG. 2 is a plan view in which a portion of FIG. 1 isillustrated in an enlarged form; FIG. 3 is a side view illustrating theinlet for an electronic tag according to this embodiment of the presentinvention; FIG. 4 is a plan view (on the back side) illustrating theinlet for an electronic tag according to this embodiment of the presentinvention; and FIG. 5 is a plan view in which a portion of FIG. 4 isillustrated in an enlarged form.

[0054] The inlet for electronic tag (which will hereinafter be called“inlet” simply) according to this embodiment constitutes a main portionof a non-contact type electronic tag equipped with antennas forreceiving microwaves. This inlet 1 has an antenna 3 made of a Cu foiladhered onto one surface of a long rectangular insulating film 2, and asemiconductor chip 5 connected to the antenna 3 while being sealed, onthe surface and side surfaces of the semiconductor chip, with a pottingresin 4. On the one surface (the surface on which the antenna 3 isformed) of the insulating film 2, a cover film 6 for protecting theantenna 3 or the semiconductor chip 5 is laminated as needed.

[0055] The antenna 3 along the long side direction of the insulatingfilm 2 is, for example, 56 mm and its length is optimized so as toefficiently receive microwaves having a wavelength of 2.45 GHz. Thewidth of the antenna 3 is 3 mm and is optimized to attain both a sizereduction and maintenance of the strength of the inlet 1.

[0056] At the approximate center of the antenna 3, an L-shape slit 7having one end reaching the outer edge of the antenna 3 is formed. Inthis slit 7, the semiconductor chip 5 sealed with the potting resin 4 ismounted.

[0057]FIGS. 6 and 7 are each an enlarged plan view illustrating thevicinity of the center of the antenna 3 at which the slit 7 has beenformed. FIG. 6 and FIG. 7 illustrate the surface side and back side ofthe inlet 1, respectively. From these drawings, the potting resin 4 forsealing the semiconductor chip 5 therewith and cover film 6 are omitted.

[0058] As illustrated, in the slit 7, a device hole 8 is formed bycutting out a portion of the insulating film 2. The semiconductor chip 5is disposed at the center of this device hole 8. The device hole 8 is,for example, 0.8 mm by 0.8 mm, while the semiconductor chip 5 is, forexample, 0.48 mm by 0.48 mm.

[0059] As illustrated in FIG. 6, over the main surface of thesemiconductor chip 5, for example, four Au bumps 9 a, 9 b, 9 c and 9 dare formed. To these Au bumps 9 a, 9 b, 9 c and 9 d, leads 10 formedintegral with the antenna 3 and having one end extending inside of thedevice hole 8 are connected.

[0060] Of the four leads 10, two leads 10 extend to the inside of thedevice hole 8 from one half of the antenna 3 divided by the slit 7 andare electrically connected to the Au bumps 9 a and 9 c of thesemiconductor chip 5. The other two leads 10 extend inside of the devicehole 8 from the other half of the antenna 3 and are electricallyconnected to the Au bumps 9 b and 9 d of the semiconductor chip 5.

[0061]FIG. 8 is a plan view illustrating the layout of the four Au bumps9 a, 9 b, 9 c and 9 d formed over the main surface of the semiconductorchip 5; FIG. 9 is an enlarged cross-sectional view of the vicinity ofthe Au bump 9 a; FIG. 10 is an enlarged cross-sectional view of thevicinity of the Au bump 9 c; and FIG. 11 is a block diagram of a circuitformed over the semiconductor chip 5.

[0062] The semiconductor chip 5 is made of a single crystal siliconsubstrate having a thickness of about 0.15 mm and has, on the mainsurface thereof, a circuit made of, for example, arectifier·transmitter, clock extractor, selector, counter and ROM. TheROM has a memory capacity of 128 bit and is capable of storing a highercapacity of data compared with a storage medium such as bar code.Another advantage of the ROM over the bar code is that data stored inROM cannot easily be falsified compared with the data stored in the barcode.

[0063] Over the main surface of the semiconductor chip 5 having theabove-described circuit formed thereon, four Au bumps 9 a, 9 b, 9 c and9 d are formed. These four Au bumps 9 a, 9 b, 9 c and 9 d exist on apair of virtual diagonals as illustrated by the chain double-dashed lineof FIG. 8 and at the same time, they are disposed so that theirdistances from the intersect of these diagonals will be substantiallyequal each other. These Au bumps 9 a, 9 b, 9 c and 9 d are formed, forexample, by the known electroplating method and their height is, forexample, about 15 μm.

[0064] The layout of these Au bumps 9 a, 9 b, 9 c and 9 d is not limitedto that illustrated in FIG. 8, but that facilitating balancing against aweight increase upon chip connection is preferred. For example, in aplane layout, a polygon formed by the tangent lines of Au bumps ispreferably disposed so that it surrounds the center of the chip.

[0065] Among the four Au bumps 9 a, 9 b, 9 c and 9 d, the Au bump 9 a,for example, constitutes an input terminal of the circuit illustrated inFIG. 11 and the Au bump 9 b constitutes a GND terminal. The remainingtwo Au bumps 9 c and 9 d constitute a dummy bump which is not connectedto the above-described circuit.

[0066] As illustrated in FIG. 9, the Au bump 9 a constituting the inputterminal of the circuit is formed over an uppermost-level metalinterconnect 22 exposed by etching of a passivation film 20 covering themain surface of the semiconductor chip 5 and a polyimide resin 21.Between the Au bump 9 a and the uppermost-level metal interconnect 22, abarrier metal film 23 is formed in order to heighten the adhesive forcetherebetween. The passivation film 20 is made of, for example, alaminate of a silicon oxide film and a silicon nitride film, while theuppermost-level metal interconnect 22 is made of, for example, an Alalloy film. The barrier metal film 23 is made of, for example, a Ti filmhaving a high adhesive force to the Al alloy film and a Pd film having ahigh adhesive force to the Au bump 9 a. The Au bump 9 b constituting theGND terminal of the circuit and the uppermost-level metal interconnect22 also have a similar constitution at the connection therebetween,which however is not illustrated here. As illustrated in FIG. 10, the Aubump 9 c (and 9 d) constituting a dummy bump is connected to the metallayer 24 formed over the same interconnect layer with theuppermost-level metal interconnect 22. This metal layer 24 however isnot connected to the above-described circuit.

[0067] Thus, in the inlet 1 of this Embodiment, the slit 7 having oneend reaching the outer edge of the antenna 3 is disposed in a portion ofthe antenna 3 formed over one surface of the insulating film 2; and theinput terminal (Au bump 9 a) of the semiconductor chip 5 is connected toone half of the antenna 3 divided into two by the slit 7, while the GNDterminal (Au bump 9 b) of the semiconductor chip 5 is connected to theother half. This constitution makes it possible to increase the actualeffective length of the antenna 3, thereby reducing the size of theinlet 1 while keeping a necessary antenna length.

[0068] In the inlet 1 of this Embodiment, Au bumps 9 a and 9 bconstituting the terminals of the circuit and dummy Au bumps 9 c and 9 dare disposed on the main surface of the semiconductor chip 5, and thesefour Au bumps 9 a, 9 b, 9 c and 9 d are connected to the correspondingleads 10 of the antenna 3, respectively. By this constitution, theeffective contact area of the Au bumps with the leads 10 can be madegreater than the constitution in which only the two Au bumps 9 a and 9 bconnected to the circuit are connected to the corresponding leads 10,leading to an improvement in the adhesion strength between the Au bumpsand leads 10, that is, connection reliability of them. In addition, bydisposing the four Au bumps 9 a, 9 b, 9 c and 9 d on the main surface ofthe semiconductor chip 5 according to the layout as illustrated in FIG.8, the semiconductor chip 5 never leans to the insulating film 2 whenthe leads 10 are connected to the Au bumps 9 a, 9 b, 9 c and 9 d. Thismakes it possible to seal the semiconductor chip 5 with the pottingresin 4 without failure, resulting in an improvement in the productionyield of the inlet 1.

[0069] A manufacturing process of the inlet 1 having the above-describedconstitution will next be described based on FIGS. 12 to 20.

[0070]FIG. 12 is a plan view illustrating an insulating film 2 to beused for the manufacture of the inlet; and FIG. 13 is a plan view inwhich a portion of FIG. 12 is illustrated in an enlarged form.

[0071] As illustrated, the insulating film 2 is carried in themanufacturing step of the inlet 1 while being wound onto a reel 25. Onone surface of this insulating film 2, a number of antennas 3 are formedin advance at regular intervals. These antennas 3 may each be formed,for example, by the following manner. A Cu foil of thickness of about 18μm is adhered onto one surface of the insulating film 2, followed byetching the Cu foil into the shape of the antenna 3. At this time, aslit 7 and leads 10 as described above are formed in each of theantennas 3. The surface of each lead 10 is then subjected to Sn (tin)plating. In order to form a thinner insulating film and antenna, it isonly necessary to form a first Cu film by sputtering on the surface ofan insulating film of thickness of about 38 μm, forming a second Cu filmthicker than the first Cu film by electroplating with the first Cu filmas a seed layer and then patterning these first and second Cu films.

[0072] The insulating film 2 meets the standards of a film carrier tape.It is, for example, made of a polyimide resin film of 50 μm or 70 mmwide and 75 μm thick, and has, in one portion of the film, a device hole8 as illustrated above in FIGS. 6 and 7. On both sides of the insulatingfilm 2, sprocket holes 26 for carrying the insulating film 2 are formedat regular intervals. These device hole and sprocket holes 26 are eachformed by punching out a portion of the insulating film 2.

[0073] As illustrated in FIG. 14, the reel 25 is attached to an innerlead bonder 30 equipped with a bonding stage 31 and a bonding tool 32and while moving the insulating film 2 along the upper surface of thebonding stage 31, the semiconductor chip 5 is connected to the antenna3.

[0074] The antenna 3 is connected to the semiconductor chip 5 bymounting, as illustrated in FIG. 15 (fragmentary enlarged view of FIG.14), the semiconductor chip 5 on the bonding stage 31 heated to about100° C., positioning the device hole 8 of the insulating film 2 directlyabove the semiconductor chip 5, and pressing the bonding tool 32 heatedto about 400° C. against the upper surface of the leads 10 protrudedinside of the device hole 8, thereby bringing the Au bumps (9 a to 9 d)in contact with the leads 10. At this time, a predetermined load isapplied to the bonding tool 32 for about 2 seconds, whereby an Au—Sneutectic alloy layer is formed at the interface between the Sn platingformed over the surface of the leads 10 and Au bumps (9 a to 9 d) andthe Au bumps (9 a to 9 d) and leads 10 are adhered, respectively.

[0075] On the bonding stage 31, another semiconductor chip 5 is mounted.After the insulating film 2 is moved by one pitch of the antenna 3, thissemiconductor chip 5 is connected to the antenna 3 in a similarprocedure to that described above. The semiconductor chip 5 is thenconnected to all the antennas 3 formed in the insulating film 2 byrepeating the above-described procedure. After completion of theconnecting work of the semiconductor chips 5 and the antennas 3, theinsulating film 2 is carried, to the subsequent resin sealing step, inthe form wound onto the reel 25.

[0076] In order to improve connection reliability between the Au bumps(9 a to 9 d) and the corresponding leads 10, it is recommended to extendthe four leads 10 in a direction perpendicular to the long sidedirection of the antenna 3 as illustrated in FIG. 16. When the fourleads 10 are extended in parallel with the long side direction of theantenna 3 as illustrated in FIG. 17, a strong tensile stress acts on thejoint between the Au bumps (9 a to 9 d) and the leads 10 by bending thecompleted inlet 1, presumably causing a deterioration in the connectionreliability between them.

[0077] In the resin sealing step of the semiconductor chip 5, asillustrated in FIGS. 18 and 19, a potting resin 4 is fed, by using adispenser 33, to the upper and side surfaces of the semiconductor chip 5mounted inside of the device hole 8, followed by baking the pottingresin 4 in a heating furnace. Also in this resin sealing step, thepotting resin 4 is fed and baked while moving the insulating film 2,which is however not illustrated. The insulating film 2 which hasfinished the resin sealing work is carried in the form wound onto thereel 25 to the subsequent inspection step, by which the connection stateof the semiconductor chip 5 and antenna 3 and the appearance areinspected. Since a number of the antennas 3 formed in the insulatingfilm 2 are electrically separated from each other, a continuity testbetween the respective antennas 3 and semiconductor chips 5 can beperformed readily. Then, a cover film 6 (refer to FIG. 3) is stacked onthe one surface of the insulating film 2 (on which the antenna 3 hasbeen formed), whereby the manufacturing steps of the inlet 1 arecompleted.

[0078] The inlet 1 thus manufactured is then packed in the form woundonto the reel 25 as illustrated in FIG. 20 and then shipped tocustomers.

[0079] The customer who has purchased the reel of the inlet 1 then cutsthe insulating film into each inlet 1 as shown in FIGS. 1 to 5. Theresulting inlet 1 is combined with another member, whereby an electronictag is manufactured. In FIG. 21, illustrated is an example of anelectronic tag obtained by adhering a double-faced adhesive tape ontothe back side of the inlet 1 and then, attached to the surface of acommodity such as expense sheet 34.

[0080] According to this embodiment, the antenna 3 is made of a thin Cufoil adhered to one surface of the flexible insulating film 2, so thatit is possible to actualize the inlet 1 which is thin and rich inflexibility compared with an inlet having an antenna using Cu as a basematerial. In addition, the terminals (Au bumps 9 a and 9 b) of thesemiconductor chip 5 are directly connected to the leads 10 formedintegral with the antenna 3, respectively, so that compared with aninlet formed by connecting the antenna 3 and semiconductor chip 5 via abonding wire, the inlet 1 of this embodiment can be made thinner by thethickness equivalent to the loop of the bonding wire. By the use of theinsulating film 2 in which a number of antennas 3 have been formed atregular intervals, the manufacture of the inlet 1, more specifically,connection of the antenna 3 with the semiconductor chip 5, sealing ofthe semiconductor chip 5 with a resin, inspection and shipment, can beperformed consistently.

[0081] The semiconductor chip 5 is disposed in the device hole 8 of theinsulating film and the leads 10 and the terminals of the semiconductorchip 5 are connected inside of the device hole 8, which facilitates boththe visual inspection at the connected part between the leads 10 and theterminals, and the protection of the connected part between the leads 10and the terminals by filling with the potting resin 4.

[0082] In the above-described embodiment, the inlet 1 is manufacturedusing the insulating film 2 having the device hole 8 formed therein. Forexample, as illustrated in FIG. 22, it is also possible to form theantenna 3 integral with the leads 10 on one surface of the insulatingfilm 12 free of the device hole 8 by the above-described method,followed by connection of the terminals (Au bumps 9 a and 9 b) of thesemiconductor chip 5 to the leads 10. In this case, after the leads 10are connected to the terminals (Au bumps 9 a and 9 b), an underfillresin 13 is filled in a space between the leads 10 and the terminals (Aubumps 9 a and 9 b) as illustrated in FIG. 23.

[0083] Use of the above-described insulating film 12 enables thefailure-free connection between leads 10 and terminals (Au bumps 9 a and9 b) compared with the use of the insulating film 2 having the devicehole 8 formed therein, which makes it possible to improve the connectionreliability between the leads and terminals and therefore, omit thedummy bumps (9 c and 9 d). When the insulating film 12 is used, however,the connected part between the leads 10 and the terminals (Au bumps 9 aand 9 b) cannot be observed visually from the back side of theinsulating film 12, so that the visual inspection method needs somemodification. In addition, a reliable filling technique is required forfilling a markedly narrow space between the leads 10 and terminals (Aubumps 9 a and 9 b) with the underfill resin 13.

[0084] In the above-described embodiment, the antenna 3 is formed usinga Cu foil adhered to the insulating film 2 made of a polyimide resin,but the cost of materials used for the inlet 1 can be reduced byconstituting the antenna 3 from an Al (aluminum) foil adhered to onesurface of the insulating film 2 or constituting the insulating film 2from a resin (for example, polyethylene terephthalate) less expensivethan the polyimide resin. When the antenna 3 is made of an Al foil, itis preferred to connect the Au bumps (9 a to 9 d) of the semiconductorchip 5 to the antenna 3 by forming an Au/Al bond using ultrasonic wavesand heating in combination.

[0085] (Embodiment 2)

[0086] In Embodiment 1, the inlet 1 was manufactured using theinsulating film 2 in which the device hole 8 had been formed, while inthis Embodiment, one example of a manufacturing process of a COF (ChipOn Film) type inlet using an insulating film 12 free of a device hole asillustrated in FIG. 22 or 23 will be described.

[0087]FIG. 24 is a plan view illustrating a portion of an insulatingfilm 12 to be used for the manufacture of a COF type inlet. Theinsulating film 12 is made of a polyimide resin film as thin as about 38μm and on one surface of the film, a number of antennas 14 having a slit15 disposed therein are formed at regular intervals. The antennas 14 areeach made of a metal film composed mainly of Cu.

[0088] The above-described antenna 14 is formed by forming a Cu film asthin as 0.1 μm or less on the surface of the insulting film 12 bysputtering, allowing a Cu film of thickness of about 9 μm to grow overthe surface of the resulting Cu film by electroplating, pattering theseCu films into the shape of the antenna 14 by photolithography, andforming an Sn film of thickness of about 0.46 μm over the patternedfilms by electroless plating.

[0089] The insulating film 12 having the antenna 14 formed thereon bythe above-described method is characterized by that compared with theinsulating film 2 of Embodiment 1 to which a Cu foil was adhered to formthe antenna therein, it is thin, is rich in flexibility, and hasextremely high bending strength, because the Cu film constituting theantenna 14 is thin and the Cu film is formed over the surface of theinsulating film 12 without using an adhesive.

[0090]FIG. 25 is an enlarged plan view illustrating the vicinity of thecenter of the antenna 14. Almost at the center of the antenna 14, anL-shaped slit 15 having one end reaching the outer edge of the antenna14 is disposed. At the corner of this slit 15, a rectangular cutout 16formed by removing the Cu film constituting the antenna 14 to expose theinsulating film 12 is disposed. Inside of this cutout 16, four leadpatterns 17 integral with the antenna 14 and having an end extending ina direction of the corner portion of the slit 15 are formed. These fourlead patterns 17 have the same area. The slit 15, cutout 16 and leadpatterns 17 are formed simultaneously with the pattering of the Cu filminto the shape of the antenna 14.

[0091] The COF type inlet using such an insulating film 12 will bemanufactured in accordance with the flow illustrated in FIG. 26.

[0092] First, a semiconductor chip 5 obtained by dicing an Au bump waferand an insulating film having an antenna 14 formed therein as describedabove are prepared. The semiconductor chip 5 is similar to that employedin Embodiment 1 (refer to FIGS. 8 to 11). The insulating film 12 is,similar to that in Embodiment 1, carried in a production line in theform wound onto a reel.

[0093] As illustrated in FIG. 27, a reel 25 is attached to an inner leadbonder 30 equipped with a bonding stage 31 and a bonding tool 32 andconnection (lead bonding) of the antenna 14 and the semiconductor chip 5is performed while moving the insulating film 12 along the upper surfaceof the bonding stage 31.

[0094] Described specifically, as illustrated in FIG. 28, thesemiconductor chip 5 is mounted on the bonding stage 31 heated to about450° C. After positioning the lead patterns 17 of the antenna 14directly above the semiconductor chip 5, the bonding tool 32 heated toabout 100° C. is pressed against the upper surface of the insulatingfilm 12 to bring the Au bumps (9 a to 9 d) into contact with the leadpatterns 17. At this time, a predetermined load is applied to thebonding tool 32 for about 2 seconds, whereby an Au—Sn eutectic alloylayer is formed at the interface between the Sn plating formed over thesurface of the lead patterns 17 and Au bumps (9 a to 9 d), and the Aubumps (9 a to 9 d) and lead patterns 17 are adhered, respectively.

[0095]FIG. 29 is a plain view illustrating how the Au bumps (9 a to 9 d)of the semiconductor chip 5 and lead patterns 17 are overlapped. In thisembodiment, the cutout 16 is formed in a portion of the antenna 14 andfour lead patterns 17 extending inside of this cutout 16 are connectedwith the Au bumps (9 a to 9 d), which is effective for heightening theconnection reliability of the antenna 14 and the semiconductor chip 5because of the reasons which will be described below.

[0096] When neither the cutout 16 nor lead pattern 17 is formed at thecorner of the slit 15 of the antenna 14, the Au bumps (9 a to 9 d) ofthe semiconductor chip 5 are connected to the four sites of the antenna14 existing on different sides of the slit 15. In such a case, however,the Cu film pattern formed around the Au bumps (9 a to 9 d) differs,depending on the position of the Au bumps (9 a to 9 d). This leads to adifference in the heat diffusion resistance (in the example illustratedin FIG. 30, a heat diffusion channel around the side to which the Aubumps 9 a and 9 c are connected is narrower than that around the side towhich the Au bumps 9 b and 9 d are connected), so that upon bonding, aheat resistance in the heat diffusion channel becomes smaller and a heatdiffusion amount therein becomes greater in the side having a wider heatdiffusion channel (the side to which the Au bumps 9 b and 9 d areconnected) than in the side having a narrower heat diffusion channel(the side to which the Au bumps 9 a and 9 c are connected).

[0097] As a result, the surface temperature of the antenna 14 lowers onthe side having a wider heat diffusion channel, which preventssufficient formation of an Au—Sn eutectic alloy layer at the interfacebetween the Au bumps (9 b and 9 d) and antenna 14, leading to adeterioration in the adhesive force therebetween. When the antenna 14and Au bumps (9 a to 9 d) are connected, for example, at positions asillustrated in FIG. 31, adhesive force with the antenna 14 becomes lowerat the three Au bumps (9 b, 9 c and 9 d) which are brought into contactwith the antenna 14 on the side having a wider heat diffusion channelthan at the one Au bump 9 a brought into contact with the antenna 14 onthe side having a narrower heat diffusion channel.

[0098] If the temperature of the bonding stage 3 or bonding tool 32 isheightened in anticipation of a lowering in the surface temperature ofthe antenna 14 on the side having a wider heat diffusion channel, theinsulating film 12 having no device hole 8 different from the insulatingfilm 2 employed in Embodiment 1 is exposed, at the chip mounting regionof the film 12, to high temperatures and undergoes thermal deformation.The product thus obtained inevitably becomes defective.

[0099] On the other hand, when the cutout 16 and lead patterns 17 areformed as described above in the chip mounting region of the antenna 14and these lead patterns 17 are connected with the Au bumps (9 a to 9 d),a heat diffusion channel from the lead patterns 17 is narrowed by thecutout so that upon bonding, a heat diffusion amount from the leadpatterns 17 towards the antenna 14 decreases. In addition, since heatdiffusion channels from lead patterns are almost uniformly narrowed bythe cutout, the temperature is almost equal at the respective jointsbetween the four Au bumps (9 a to 9 d) and lead patterns 17.

[0100] The smaller the area of the lead pattern 17, the less the heatdiffusion amount from the lead pattern 17 to the antenna 14. Excessivelysmall diffusion amounts reduce a contact area with the Au bumps (9 a to9 d), leading to a reduction in the bonding strength between the Aubumps and the antenna. In order to suppress the heat diffusion amountand keep a certain contact area, the width of the lead pattern 17 may beset at a size slightly greater than the diameter of the Au bumps (9 a to9 d) (the size meaning the diameter of the Au bump+alignment margin).

[0101] By forming the cutout 16 and lead patterns 17 in the chipmounting region of the antenna 14 and connecting the lead patterns 17and Au bumps (9 a to 9 d), it is possible to suppress a temperaturedecrease at the joints between the Au bumps (9 a to 9 d) and leadpatterns 17 upon bonding and at the same time, to make the temperaturesuniform at the joints between the four Au bumps (9 a to 9 d) and thelead patterns 17. This makes it possible to form a uniform Au—Sneutectic alloy layer at the interface between the Au bumps (9 a to 9 d)and lead patterns 17 and heighten the bonding strength therebetween,leading to an improvement in the connection reliability between theantenna 14 and the semiconductor chip 15.

[0102] The shape of the cutout 16 or lead patterns 17 disposed in thechip mounting region of the antenna 14 is not limited to theabove-described hoe type or stag type, but any shape can be adoptedinsofar as it prevents a temperature decrease at the position to bebrought into contact with the four Au bumps (9 a to 9 d) and at the sametime it actualizes temperature uniformity.

[0103] An underfill resin 41 is then filled by using a dispenser 40 in aspace between the lower surface of the semiconductor chip 5 and theinsulating film 12 (and antenna 14) as illustrated in FIG. 32, followedby curing of the underfill resin 41 in a heating furnace. This curing ofthe underfill resin 41 in a heating furnace is performed first bysemi-curing the underfill resin 41, winding the insulating film 12 ontoa reel 25, carrying the reel 25 in the heating furnace to completelycure the underfill resin 41. Prior to winding of the insulating film 12onto the reel 25 after semi-curing of the underfill resin 41, inspectionto judge whether the connection between the antenna 14 and semiconductorchip 5 is good or not may be carried out.

[0104] As illustrated in FIG. 33, the underfill resin 41 filled in thelower surface of the semiconductor chip 5 is, at the outermost edge ofthe resin, preferably brought into contact with the antenna 14 outsideof the cutout 16. In short, the diameter of the underfill resin 41 isdesirably greater than that of the cutout 16. On the other hand, whenthe diameter of the underfill resin 41 is smaller than that of thecutout 16 as illustrated in FIG. 34, the insulating film 12 covered withneither the antenna 14 nor the underfill resin 41 is exposed partiallyinside of the cutout 16.

[0105] Since the insulating film 12 is considerably thin, a stress isapplied to a thin portion of the completed inlet, if any, upon bendingof the inlet, which presumably causes peeling of the semiconductor chip5 from the antenna 14. The insulating film 12 inside of the cutout 16 istherefore desirably covered with the underfill resin 41 as illustratedin FIG. 32. At this time, when the diameter of the cutout 16 is madesmaller than that of the semiconductor chip 5, the insulating film 12inside of the cutout 16 is covered with the underfill resin 41 and thesemiconductor chip 5, leading to a further improvement in the filmstrength in the vicinity of the joint between the semiconductor chip 5and antenna 14.

[0106] Upon formation of the cutout 16 and lead patterns 17 in theantenna 14, their shape or size is preferably designed in considerationof the size of the underfill resin 41 or semiconductor chip 5.

[0107] The underfill resin 41 is made of an organic resin such as epoxyso that it is recommended to form an organic resin film such aspolyimide resin film on the uppermost surface of the semiconductor chip5. This reinforces the adhesive force between the underfill resin 41 andthe semiconductor chip 5, leading to an improvement in the bendingstrength (connection strength between the semiconductor chip 5 andantenna 14) of the completed inlet.

[0108] With the completion of the resin sealing of the semiconductorchip 5, the manufacturing step of the inlet is almost finished. Aftervisual inspection step and final sorting step, the COF type inlet thusmanufactured is packed in the form wound onto a reel, and shipped tocustomers, where the inlet is cut and separated from the insulating film12.

[0109] This Embodiment thus enables manufacture of a COF type inletwhich is thin, has a small size, and has considerably high bendingstrength. It is therefore possible to provide an inlet which canwithstand the use even under poor conditions exposed to heat, moistureor mechanical stress.

[0110] The present invention made by the present inventors was describedspecifically based on some embodiments. It should however be borne inmind that the present invention is not limited to or by them, but can bemodified within an extent not departing from the gist of the invention.

[0111] Advantages available by the typical inventions, among theinventions disclosed by the present application, will next be describedbriefly.

[0112] According to one embodiment of the present invention, an inletfor an electronic tag which is thin and has high bending strength can beactualized at a low cost.

What is claimed is:
 1. An inlet for an electronic tag comprising: aninsulating film; antennas each made of a conductor layer and formed overone surface of the insulating film; a slit formed in a portion of eachof the antennas and having one end extending to the outer edge of theantenna; a semiconductor chip electrically connected to each of theantennas via a plurality of bump electrodes; and a resin for sealing thesemiconductor chip therewith.
 2. An inlet for an electronic tagaccording to claim 1, wherein the antennas each made of a conductorlayer are formed by patterning a copper foil or an aluminum foil formedover one surface of the insulating film.
 3. An inlet for an electronictag according to claim 1, wherein the semiconductor chip is disposedinside of a device hole formed in the insulating film and is sealed witha potting resin.
 4. An inlet for an electronic tag according to claim 1,wherein the plurality of bump electrodes for electrically connectingeach of the antennas with the semiconductor chip include a dummy bumpnot electrically connected to a circuit in the semiconductor chip.
 5. Aninlet for an electronic tag according to claim 4, wherein the pluralityof bump electrodes have one bump electrode constituting an inputterminal of the circuit, another bump electrode constituting a GNDterminal of the circuit, and two dummy bump electrodes not electricallyconnected to the circuit.
 6. An inlet for an electronic tag according toclaim 5, wherein the bump electrode constituting the input terminal ofthe circuit is electrically connected to one half of each of theantennas obtained by dividing the antenna into two by the slit and theanother bump electrode constituting the GND terminal of the circuit iselectrically connected to the other half of the antenna.
 7. An inlet foran electronic tag according to claim 1, wherein the plurality of bumpelectrodes are electrically connected to leads formed integral with eachof the antennas, respectively, and the leads each extends in a directionperpendicular to the long side direction of each of the antennas.
 8. Aninlet for an electronic tag according to claim 1, wherein a cover filmfor protecting each of the antennas and the semiconductor chip isstacked over the one surface of the insulating film.
 9. A manufacturingprocess of an inlet for an electronic tag comprising: an insulatingfilm; antennas made of a conductor layer and formed over one surface ofthe insulating film; a slit formed in a portion of each of the antennasand having one end extending toward the outer edge of the antenna; asemiconductor chip electrically connected to each of the antennas via aplurality of bump electrodes; and a resin for sealing the semiconductorchip therewith, comprising the steps of: (a) preparing a long insulatingfilm in which a plurality of antennas made of a conductor layer areformed so as to be separated from each other; (b) connecting asemiconductor chip to each of the plurality of antennas formed in theinsulating film; (c) sealing, with a resin, the semiconductor chipconnected to each of the plurality of antennas; and (d) inspecting thequality of the inlet for an electronic tag manufactured by the steps(a), (b) and (c), wherein the long insulating film is carried from thestep (a) to the step (d) in the form wound onto a reel.
 10. Amanufacturing process of an inlet for an electronic tag according toclaim 9, further comprising, after the step (d), a step of shipping thelong insulating film in the form wound onto a reel.
 11. An inlet for anelectronic tag comprising: an insulating film; antennas each made of aconductor layer and formed over one surface of the insulating film; aslit formed in a portion of each of the antennas and having one endextending toward the outer edge of the antenna; a semiconductor chipelectrically connected to each of the antennas via a plurality of bumpelectrodes; and a resin for sealing the semiconductor chip therewith,wherein a cutout is disposed in a portion of each of the antennas forexposing the insulating film, wherein a plurality of lead patterns whichare each made of the conductor film and has one end connected to each ofthe antennas and the other end extending inside of the cutout are formedinside of the cutout, and wherein the plurality of bump electrodes areconnected to the surfaces of the lead patterns formed at positionscorresponding to the bump electrodes, respectively.
 12. An inlet for anelectronic tag according to claim 11, wherein the conductor film is madeof a copper film formed over one surface of the insulating film and atin plating layer formed over the surface of the copper film, and thebump electrodes are metal bumps.
 13. An inlet for an electronic tagaccording to claim 11, wherein the plurality of bump electrodes includea bump electrode constituting an input terminal of a circuit formed overthe semiconductor chip, another bump electrode constituting a GNDterminal of the circuit, and a dummy bump electrode not electricallyconnected to the circuit.
 14. An inlet for an electronic tag accordingto claim 11, wherein the plurality of lead patterns have the same area.15. An inlet for an electronic tag according to claim 11, wherein thewidth of each of the plurality of lead patterns is greater than thediameter of the bump electrode.
 16. An inlet for an electronic tagaccording to claim 11, wherein an organic resin film is formed over thesurface of the semiconductor chip.
 17. An inlet for an electronic tagaccording to claim 11, wherein the resin for sealing the semiconductorchip is, at the outermost edge of the resin, brought into contact withthe antenna outside the cutout.
 18. An inlet for an electronic tagaccording to claim 17, wherein the diameter of the semiconductor chip isgreater than that of the cutout.